At its 2022 Expertise Symposium, TSMC formally unveiled its N2 (2 nm class) fabrication know-how, which is slated to enter manufacturing a while in 2025 and will likely be TSMC’s first node to make use of their nanosheet-based gate-all-around field-effect transistors (GAAFETs). The brand new node will allow chip designers to considerably scale back the ability consumption of their merchandise, however the velocity and transistor density enhancements appear significantly much less tangible.
TSMC’s N2 is a brand-new platform that extensively makes use of EUV lithography and introduces GAAFETs (which TSMC calls nanosheet transistors) in addition to bottom energy supply. The brand new gate-all-around transistor construction guarantees well-published benefits, comparable to drastically lowered leakage present (now that the gates are round all 4 sides of the channel) in addition to skill to regulate channel width to extend efficiency or decrease energy consumption. As for the bottom energy rail, it’s usually designed to allow higher energy supply to transistors, providing an answer to the issue of accelerating resistances within the back-end-of-line (BEOL). The brand new energy supply is slated to extend transistor efficiency and decrease energy consumption.
From characteristic set standpoint, TSMC’s N2 seems to be like a really promising know-how. As for precise numbers, TSMC guarantees that N2 will permit chip designers to extend efficiency by 10% to fifteen% on the similar energy and transistor rely, or scale back energy consumption on the similar frequency and complexity by 25% ~ 30%, all of the whereas rising chip density by over 1.1-fold when in comparison with N3E node.
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*Chip density revealed by TSMC displays ‘combined’ chip density consisting of fifty% logic, 30% SRAM, and 20% analog.
Versus N3E, the efficiency enhancements and energy reductions enabled by TSMC’s N2 node are in keeping with what the foundry’s new nodes usually usher in. However the so-called chip density enhancements (which ought to mirror transistor density good points) are just a bit over 10%, which isn’t notably inspiring, particularly contemplating that N3E already affords a barely decrease transistor density when in comparison with vanilla N3. Preserving in thoughts that SRAM and analog circuits barely scale lately, mediocre enhancements in transistor density of precise chips ought to in all probability be anticipated lately. Nonetheless, a chip density enchancment of 10% in about three years is definitely not nice information for GPUs and different chips that reside or die based mostly on quickly rising their transistor counts.
Taking into consideration that by the point TSMC’s N2 enters manufacturing the corporate may even have the density-optimized N3S node, it could seem that the foundry can have two course of applied sciences based mostly on several types of transistors but providing very comparable transistor densities, one thing that has by no means occurred earlier than.
As typical, TSMC will supply their N2 node with numerous options and knobs to permit chip designers to optimize for issues like cellular and high-performance computing designs (word that TSMC calls HPC every thing that’s not cellular, automotive or specialty. which incorporates every thing from a low-power laptop computer CPU to a high-end compute GPU aimed toward supercomputers). Additionally, platform choices embody one thing that TSMC calls ‘chiplet integration’, which in all probability implies that TSMC allow its prospects to simply combine N2 chips into multi-chiplet packages made utilizing numerous nodes. Since transistor density scaling is slowing down and new course of applied sciences are getting costlier to make use of, multi-chiplet packages are going to turn out to be extra frequent within the coming years as builders will likely be utilizing them to optimize their designs and prices.
TSMC expects to start out threat manufacturing of chips utilizing its N2 fabrication course of generally within the second half of 2024, which implies that the know-how needs to be obtainable for prime quantity manufacturing (HVM) of economic merchandise within the second half of 2025. However, contemplating the size of recent semiconductor manufacturing cycles, it is probably extra pragmatic to count on the primary N2 chips to turn out to be obtainable both very late in 2025 or 2026, if every thing goes as deliberate.